iPDA3500

 

                   Preliminary Product Information Sheet
                            iPDA3500  

                  3x500 MS/s , DATA ACQUISITION CARD
     

      FEATURES

     APPLICATIONS

     OVERVIEW

     BLOCK DIAGRAM

     SPECIFICATIONS

  		    

                    

                   

                                    FEATURES:

  • 1500 MS/s Digitization on one channel
  • Simultaneous 500MS/s Sampling on 3 channels
  • Up to 10GS/s sampling for repetitive signals
  • 250 MHz Analog Bandwidth
  • 8/16 bit resolution
  • Up to 128 Megabytes SDRAM memory on board
  • Up to 3 Megabytes SSRAM memory on board
  • Onboard DSP capabilities with real time features
  • 40.5 dB Signal to Noise Ratio
  • 60 dB Variable Gain Input Amplifier, 0.5 dB/step
  • Programmable RF Filters
  • Internal or External Clock & Trigger
  • 12 Gb/s data transfer via LVDS serial interface
  • Optional Optical interface Link
  • 1Mb/s UART (RS-485 interface)
  •  32 bit PCI Bus Interface
  • 100MB/s Data Transfer Rate to PC Memory
  • Programmable Time Stamping
  • Up to 8 Cards in a Master/Slave System for up to 8 Simultaneous 
  • channels at 1500 MGS/s and 24 channels at 500 MS/s
  • Remote Hardware programmability’s 

                                                     APPLICATIONS

·         Laser Measurement and Testing (Wafers, Flat Panel Displays, Disks

·         EMI Detection

·         Semiconductor Testing

·         HDTV

·         Ultrasonic Medical Imaging System

·         Explosion Testing

·         Radar and sonar systems

·         Infrared Imaging

·         Non-Destructive Testing

·         High Speed Analysis

·         Video, HDTV and image processing systems

·         Industrial Ultrasound

·         Communications Link Testing

·         Imaging  

·         Deep Capture of Medical Sonography Signals.

·         LIDAR

·         Nuclear Decay Experiment and Measurement.

·         Laser Doppler Velocimetry

·         Cable TV Testing

·         Machine Vision and Inspection

·         Image Acquisition from Analog Cameras

·         Machine Monitoring

·         Analytical Instrumentation

·         Military and Aerospace

·         Acoustic Emission

·         Mass Spectrometry  

·         Communication

·         Nuclear Decay Measurement

·         CCD Imaging

·         Nuclear Ion Testing

·         Digital Oscilloscope

·         Oceanography Survey

·         Disc Drive Testing

·         Process Control Systems 

·         Time Domain Reflectometer 

·         Time Domain Analysis

·         Transient Capture

·         Time of Flight Measurement

·         Video

·         Microscope

·         Digital Spectrum Analyzer

·         Process Automation

·         Logic Analyzer

·         Scanning Laser

·         Environmental Monitoring

·         Seismic Exploration

·         Shock Wave Testing

·         Spot Weld Testing

 

                                            OVERVIEW:

The iPDA3500 card is a unique 3-channel high-speed waveform capturing systems with a flexible built-in high speed DSP core that make it one of the most flexible real-time products in the market. The card can sample all the three analog inputs simultaneously at speeds up to 400 MS/s with 8 bit resolution. The card is available with memory depth from 2MB to 128MB.

The iPDA3500 includes a digitally controlled attenuator that allows the input voltage range to be adjusted in 0.5 dB steps from 2mV p-p to 2V p-p. The gain can be fixed to be constant or can be vary dynamically related to a pre-define curve. 

The DATA transfer is done via the PCI bus in DMA transfer mode. Data transfer rates from the iPDA3500 local memory to the PC memory runs at the PCI maximum speed.
The iPDA3500 also provides the possibility to transfer data to external DSP card by LVDS interface. Sustained transfers of up to 9600 MB/s are possible.
Optical link to external devices is optionally.

The iPDA3500 is equipped with multiple acquisition and trigger modes. For single event acquisitions, the iPDA3500 is equipped with a single shot mode allowing pretrigger, normal, delayed trigger or threshold trigger storage. For multi-trigger acquisitions, segmented triggering is possible. Delayed and pretrigger features may also be used when acquiring segmented data.

The iPDA3500 board can switch the supplies ON and OFF and get into a power saving mode. The board is designed to work as a Universal board and capable of detecting the signaling environment in use, and adapting itself to that environment. It can therefore, be plugged into either 5V PCI connector type or into the 3.3V connector.

Unlike a standard PC card digitizer, the iPDA3500 include an open hardware platform that can be adapted easily to a variety of applications. The card hardware will allow more than 50% free resources for future applications.

     Remote Hardware programmability’s

Remotely upgrading software to add new enhancements or fix bugs in the code is a commonplace practice in the electronics industry today. The iPDA3500 built around a new concept that allows a remotely updating hardware. This ability means that the card features can be swapped in and out or that a new hardware features can be added or be fix remotely.

This powerful feature is unique in the industry today.

 

                             
                                                                                Block Diagram:

Click to enlarge

  Click here to large print                                                                   Click to large view 

                                               

                                SPECIFICATIONS:

 

                                

                

Input Signals

Channel 1:

Analog Input

Channel 2:

Analog Input

Channel 3:

Analog Input

External Trigger (in):

 

External Clock (in/out):

 

External Connectors:

4 LEMO 00

External Trigger

impedance:

50 ohms / 1K ohms

trigger level:

±250 mV @ 50 ohms,±2.5 V @ 1k ohm

adjustment method:

via 8 bit DAC

bandwidth:

250 MHz @ 50 ohms

coupling:

AC or DC

output trigger:

TTL synchronous with start and end of acquisition

External Clock

signal type:

ECL logic or sine/square wave input

Impedance:

50 ohms to ground1

Frequency: 

50 MHz to 500 MHz8

Amplitude: 

100 mV p-p to 2.0 V p-p

output clock:

TTL clock - quarter of the digitizer frequency

Analog Inputs

full scale voltage:

2 mV p-p to 2.0 V p-p2

impedance:

50 ohms

bandwidth :

250 MHz 1

equivalent noise:

0.5 LSB RMS (typical)

coupling:

AC or DC1

 

Digitizer

resolution:

8 or 16 bits

linearity, integral:

±0.5 LSB max.

linearity, differential:

±0.75 LSB max.

aperture width:

270 pS typical

internal clock rates:

25MHz to 500 MHz

DC Offset Voltage

8 bit DAC, ±500 mV at ADC input

 

Attenuator

range:

0 to 60 dB

steps:

0.5dB per step

Min step width

20nS

Slew Rate

30dB/20nS

control:

digital2

 

Input Signals

Channel 1:

Analog Input

Channel 2:

Analog Input

Channel 3:

Analog Input

External Trigger (in):

 

External Clock (in/out):

 

External Connectors:

4 LEMO 00

Analog Inputs

full scale voltage:

2 mV p-p to 2.0 V p-p2

impedance:

50 ohms

bandwidth :

250 MHz 1

equivalent noise:

0.5 LSB RMS (typical)

coupling:

AC or DC1

External Trigger

impedance:

50 ohms / 1K ohms

trigger level:

±250 mV @ 50 ohms, ±2.5 V @ 1k ohm

adjustment method:

via 8 bit DAC

bandwidth:

250 MHz @ 50 ohms

coupling:

AC or DC

output trigger:

TTL synchronous with start and end of acquisition

External Clock

signal type:

ECL logic or sine/square wave input

Impedance:

50 ohms to ground1

Frequency: 

50 MHz to 500 MHz8

Amplitude: 

100 mV p-p to 2.0 V p-p

output clock:

TTL clock - quarter of the digitizer frequency

DC Offset Voltage

8 bit DAC, ±500 mV at ADC input

Digitizer

resolution:

8 or 16 bits

linearity, integral:

±0.5 LSB max.

linearity, differential:

±0.75 LSB max.

aperture width:

270 pS typical

internal clock rates:

25MHz to 500 MHz

Trigger Modes

single shot:

single start trigger fills active memory

segmented:

start trigger for each memory segment

Trigger Methods

Pretrigger:

Programmable up to 1K

Delayed Trigger

delay from trigger to data storage
0 to 65K in steps of 10nS

Memory

Size:

1 or 128 Megabytes

Addressing:

via Memory Mapping or DMA

Memory Address (PC):

Plug and Play selected

DSP Link

data transfer modes:

block or packetized data

data transfer protocol:

Serial in LVDS standard

data transfer rates:

12 Gb/s max

data direction:

In and out

Optical Link

data transfer modes:

block or packetized data

data transfer protocol:

Serial

data transfer rates:

t.b.d

data direction:

In and out

Power Down Features

Off Mode:

Board Deactivated; Power usage less than t.b.d mW

Power Down:

Deactivation of acquisition circuits reduces power by 2/3

Thermal Shutdown:

Card temp. greater than 70ºC deactivates power

                                 All specifications subject to change without notice  

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